![]() Anonymous said. Library IEEE; use IEEE.STD_LOGIC_1164.all; entity sipo_behavior is port( din: in STD_LOGIC; clk: in STD_LOGIC; reset: in STD_LOGIC; dout: out STD_LOGIC_VECTOR(3 downto 0) ); end sipo_behavior; architecture sipo_behavior_arc of sipo_behavior is begin sipo: process (clk,din,reset) is variable s: std_logic_vector(3 downto 0):= '0000'; begin if (reset='1') then s:= '0000'; elsif (rising_edge (clk)) then for i in 0 to 2 loop s(i+1):= s(i); end loop end if; dout. Serial Shift/ Parallel Load Latch Clock Shift Clock Serial Input SA Parallel Inputs A−H Data Latch Contents Shift Register Contents Output QH Force Output into High Impedance State H X X X X X X X Z Load Parallel Data into Data Latch L H L, H, X a−h a−h U U Transfer Latch Contents to Shift Register L L L, H, X X X U LRN → SRN LRH. Kalender 2015 cdr.
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